IT8209R incorporates an extended PCI arbiter and a clock buffer.
The extended PCI arbiter utilizes one set of SYSGNT# and SYSREQ# to support 3 PCI Masters, so that two more PCI Masters can be supported for the system. PCISTOP# input signal is useful to facilitate the fairness arbitration.
The clock buffer provides 4 zero delay and low jitter clock sources. PCICLKI is the clock input of the clock buffer, and PCICLKOUT is the clock output fed back internally to the input of the built-in PLL to reduce the clock skew. If zero clock skew is required, PCICLKOUT and PCICLK1 to PCICLK4 must be equally loaded.
When PCICLKI input becomes inactive, IT8209R will enter power down mode. In power down mode, all clock outputs are low and other control outputs are deasserted.