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IT6113: High Speed MIPI DSI 4 Lane to 8 Lane Bridge

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  • Specification Table

  • Product Information

  • Specification Table

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Product Information

IT6113: High Speed MIPI DSI 4 Lane to 8 Lane Bridge

The IT6113 MIPI DSI video bridge is a 4-lane-in, 8-lane-out high speed data converter/splitter. It integrates a 4-lane single–link MIPI DSI receiver and an 8-lane dual-link MIPI DSI transmitter. The DSI bridge may be configured to a half-rate data converter or a full-rate data splitter for different applications.


When acting as a half-rate data converter, the 8-lane transmitter of IT6113 is capable of outputting either L/R pixels or Even/Odd pixels in the first and the second 4-lane link according to the backend panel's ability. When in splitter mode, either one of the TX links can be switched on/off independently. The RX front end of IT6113 supports a data rate of up to 2.5 Gbs per lane, enabling processing of a video signal of 2560X1600@70Hz, 2176X1536@85Hz, or other ultra-high resolution format such as WUXGA in converter mode. The TX PHY of IT6113 supports a data rate of up to 1.5 Gbs per lane.


The IT6113 is compliant with MIPI DSI Version 1.1 and MIPI D-PHY Version 1.1. It supports RGB Packed Pixel Stream 18-bit, 24-bit, 30-bit, and 36-bit format.


The IT6113 supports VRR function, so that VRR feature can be implemented in the system.


The IT6113 is configured and controlled via I2C bus, including parameter settings and low power mode command R/W.


IT6113 is packed in 48-pin 6x6 QFN package. It operates with 1.0V and 1.8V power supply.

Features

  • MIPI DSI 4-lane input, 8-lane output converter/splitter bridge
  • Supports 4-lane to 8-lane half-speed converter in L/R mode or Even/Odd mode
  • Supports 4-lane to 4-lane bypass repeater or 4-lane to 2*4-lane bypass splitter mode
  • RX D-PHY capable of operating in link rate up to 2.5 Gbs per lane, enabling support of 2560X1600@70Hz, 2176X1600 @85Hz or other video stream
  • TX D-PHY capable of operating in link rate up to 1.5 Gbs per lane
  • Maximum video frame size: 8k*4k (with RX link rate not exceeding 2.5 Gbs)
  • Compliant with MIPI DSI Version 1.1 and MIPI D-PHY Version 1.1
  • Supports MIPI RX D-PHY High Speed De-skew feature for high speed(over 1.5 Gbs) utilization as specified in D-PHY specification ver. 1.2
  • Supports MIPI DSI Packed Pixel Stream in RGB 18/24/30/36-bit format
  • Supports MIPI DSI Loosely Packed Pixel Stream in RGB 18-bit format
  • Supports MIPI DSI Low Power Command in both TX0 and TX1 output port(Commands issued by FW via I2C)
  • Supports internal MIPI DSI pattern generator for both TX0 and TX1 output port with external MCLK
  • Supports Sync Event/Sync Pulse mode
  • Supports Low Power Mode entry in all lines during V-blanking
  • Supports Lane/Polarity swap in both RX/TX sides
  • Supports Continuous-clock mode only
  • Supports DSI 4-lane per link only
  • Supports progressive mode only
  • Supports VRR function
  • Power supply: 1.0V and 1.8V
  • 48-pin (6 mm x 6 mm) QFN package
  • RoHS-compliant and Halogen-Free

Specification Table

After years of technology development, ITE has owned many types of advanced Silicon Intellectual Property (SIP) and highly integrated technology of system software/hardware.

PART NO.

PACKAGE TYPE

DESCRIPTION

FLASH SUPPORT

IT6113

48-pin QFN (6 mm x 6 mm)

High Speed MIPI DSI 4 lane to 8 lane Bridge

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